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FPGA implementation of radix 2 division with over-redundant quotient selection
Conference proceeding

FPGA implementation of radix 2 division with over-redundant quotient selection

A.A. Ibrahem, H. Elsimary, A.E. Salama and ECE-CUFE
Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442), Vol.2003-, pp.269-273
2003
DOI: https://doi.org/10.1109/ICM.2003.237827

Abstract

Application software Arithmetic Circuits Costs Fabrication Field programmable gate arrays Hardware Logic Silicon Table lookup
The flexibility of field programmable gate arrays (FPGAs) can provide arithmetic intensive applications with the benefites of custom hardware but without the high cost of custom silicon implementations. In this paper present the adaptation of radix 2 division algorithm for lookup table based FPGAs implementation. This division algorithm is well suited for IEEE 754 standard operands belonging to the range. The implementation has been done with xilinx technology and FPGA-Advantage CAD tools.

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