Abstract
Conference Title: 2017 27th International Conference on Field Programmable Logic and Applications (FPL) Conference Start Date: 2017, Sept. 4 Conference End Date: 2017, Sept. 8 Conference Location: Ghent, Belgium Process variation is increasing with each successive technology node, and it has reached the point where the worst-case timing modelling employed by current FPGA CAD tools is significantly underutilizing the available silicon. Previous studies have proposed exploiting FPGA reconfigurability to reduce this underutilization using techniques such as late binding and dynamic voltage scaling. Most of the proposed solutions require the ability to measure the target application's delay on each configured chip. To accurately measure the delay of an application on a certain chip, we must measure the delay of its speed limiting paths on this specific chip. In this paper, we present a variation-aware CAD tool that automatically generates calibration bitstreams to measure the delay of any input application. Our tool identifies the statistically critical paths of the circuit and optimally selects which paths to test such that it minimizes the chances of reporting an optimistic delay, under a constraint on the number of allowed calibration bitstreams. Experimental results across a suite of benchmarks show that with one calibration bitstream we achieve 16× lower probability of reporting an optimistic delay compared to a greedy approach. With three calibration bitstreams, we reduce the probability of optimism to two chips in a million, approximately 6,000 × lower than a greedy approach.