Abstract
Gated Pixel Convolution Neural Network (Pix-eICNN) is a computationally intensive network that is useful for generating visual data. The prediction and generating pixels is a challenging but useful task for many fields such as forensics, machine vision and robotics. However, implementing PixeICNN in edge devices is a challenging task due to learning complexity and computational limits. In this paper, we present the design of neuro-memristive circuits for computing PixelCNN cells in analog domain as a coprocessor unit in edge devices. The architecture was designed using 180nm CMOS technology and carbon-chalcogenide memristive devices. On-chip area of the proposed architecture unit is 24.756mm 2 , while power depends on the size of the input image and the configuration of the overall network. The power required to generate the images sequentially is 154.336mW.