HARDWARE IMPLEMENTATION OF FAST BLOCK MATCHING ALGORITHM IN FPGA FOR H.264/AVC

M. Kthiri; H. Loukil; I. Werda; A. Ben Atitallah; A. Samet; N. Masmoudi; IEEE

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HARDWARE IMPLEMENTATION OF FAST BLOCK MATCHING ALGORITHM IN FPGA FOR H.264/AVC

M. Kthiri, H. Loukil, I. Werda, A. Ben Atitallah, A. Samet, N. Masmoudi and IEEE

2009 6TH INTERNATIONAL MULTI-CONFERENCE ON SYSTEMS, SIGNALS AND DEVICES, VOLS 1 AND 2, p.689

01/01/2009

Abstract

Computer Science

Computer Science, Information Systems

Engineering

Engineering, Electrical & Electronic

Science & Technology

Technology

Telecommunications

Motion estimation (ME) is one of the most time-consuming parts in video encoding system, and significantly affects the output quality of an encoded sequence. In this paper, we present hardware implementation of the Large Diamond Parallel search algorithm. This hardware is designed to be used as part of a complete H.264 video coding system. This architecture is simulated and tested using VHDL and synthesized using Altera Quartus II version 5.1. Also, This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The VHDL code is verified to work at 100 MHz in ALTERA Stratix II FPGA.

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Title: HARDWARE IMPLEMENTATION OF FAST BLOCK MATCHING ALGORITHM IN FPGA FOR H.264/AVC
Creators - without role: M. Kthiri - University of Sfax
H. Loukil - University of Sfax
I. Werda - University of Sfax
A. Ben Atitallah - University of Sfax
A. Samet - University of Sfax
N. Masmoudi - University of Sfax
IEEE
Publication Details: 2009 6TH INTERNATIONAL MULTI-CONFERENCE ON SYSTEMS, SIGNALS AND DEVICES, VOLS 1 AND 2, p.689
Publisher: IEEE
Number of pages: 2
Identifiers: 9912802008331
Academic Unit: Al Jouf University; King Khalid University
Language: English
Resource Type: Conference proceeding