Abstract
This paper describes HIPED, a tool for fast power estimation of DSP algorithms given its data-flow graph representation. Each node of the DFG is characterized for low-power using LP-DSM. In order to estimate the power consumption of the DSP, HIPED computes the entropy of the data transferred between two computational nodes. The entropy, which measures the data-activity of the circuit, is subsequently used by the power macro-model to predict the power consumption of the sink node. The total power consumption is thus obtained by summing up the power consumption of each node of the DFG. HIPED is used to estimate the power consumption of a variety of DSP algorithms used in typical wireless receivers implemented in 0.35 /spl mu/m, 3.3 V CMOS process. The characterization process of arithmetic units implements both using SPL and CMOS circuit style showed that LP-DSM has lower prediction sum of error and lower error in cycle power than Gupta's algorithm. Furthermore, the simulation results using real data showed that HIPED has a very good accuracy compared to circuit level power reported by PowerMill. The observed average error of our benchmark circuits is less than 10%.