Hardware Fault Free Simulation for SOC

V.L. Hahanov; M.O. Kaminska; W. Ghribi; A.V. Hahanova

doi:10.1109/MIXDES.2007.4286197

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Conference proceeding

Hardware Fault Free Simulation for SOC

V.L. Hahanov, M.O. Kaminska, W. Ghribi and A.V. Hahanova

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems, pp.424-428

06/2007

DOI: https://doi.org/10.1109/MIXDES.2007.4286197

Abstract

Analytical models

Automatic testing

Circuit faults

Circuit simulation

Circuit testing

Discrete event simulation

Fault simulation

Hardware

Hardware embedded simulator

Hazards

Mathematical model

System testing

Test generation

Topological analysis

In the paper structure functional multi-valued hardware model of digital device is offered; two-circuits structure functional multi-valued hardware model of digital device for multiple input patterns co-simulation and multiple increasing of performance transient analysis in sequential structures is proposed; automatic model of HDL-code transmission process to data structure for digital system on chip analysis and verification with hardware is proposed.

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Details

Title: Hardware Fault Free Simulation for SOC
Creators - without role: V.L. Hahanov - Kharkiv National University of Radio Electronics
M.O. Kaminska - Kharkiv National University of Radio Electronics
W. Ghribi - Kharkiv National University of Radio Electronics
A.V. Hahanova - Kharkiv National University of Radio Electronics
Publication Details: 2007 14th International Conference on Mixed Design of Integrated Circuits and Systems, pp.424-428
Publisher: IEEE
Identifiers: 9923979408331
Academic Unit: King Khalid University
Language: English
Resource Type: Conference proceeding