Abstract
Despite widespread applications in the fields of electrical and computer engineering, complex numbers, to a large degree, have been relegated in computer arithmetic as distant relatives of real numbers and treated in the same manner. Arithmetic operations involving complex numbers are accomplished by the application of divide-and-conquer technique whereby each complex number is broken-up into its real and imaginary parts and then the operation - on each part is performed as if part of real arithmetic. The overall result of complex operation is then obtained by combining the individual results of both the real and imaginary parts. This technique forsakes the advantages inherent in the use of complex numbers and, answering to the need of representing a given complex number as a single unit, complex binary numbers with bases (-1+j) and (-1-j) have been proposed in the literature. In this paper, we have presented hardware designs, FPGA-implementation statistics, and performance evaluations of nibble-size adders for complex binary numbers.