Abstract
In this paper we present a hardware realization of a simplified blood-pressure regulation mechanism. The mechanism has been proposed and then modeled by using Hardware Description Language (VHDL). After verifying the simulation results, Computer Aided Design (CAD) tools are implemented to download the simulation into a Xilinx FPGAs chip. The chip has been tested by. comparing the behavior of the signals on its pins representing the blood pressure and other parameters of the mechanism with that of the proposed mechanism. Our results show that the chip mimics the mechanism.