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Harmonics elimination technique applied to an NPC topology three level inverter used as static VAr compensator
Conference proceeding

Harmonics elimination technique applied to an NPC topology three level inverter used as static VAr compensator

M. Benghanem, A. Draou, A. Tahri and IEEE
IEEE 2002 28th Annual Conference of the Industrial Electronics Society. IECON 02, Vol.1, pp.526-531 vol.1
2002
DOI: https://doi.org/10.1109/IECON.2002.1187563

Abstract

Circuit topology Frequency Leg Nonlinear equations Pulse inverters Pulse width modulation Pulse width modulation inverters Static VAr compensators Switches Voltage control
In this paper the use of harmonics elimination method applied to a three level inverter is reported. The method used to calculate the switching angles is clearly shown and discussed. Simulations results using Pspice program and experimental results are carried out to validate the mathematical model. Finally, we applied this harmonics elimination method to control an advanced static VAr compensator (ASVC) which uses a three level voltage source inverter.

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