High-level design for image processing on FPGA using Xilinx AccelDSP

Yahia Said; Taoufik Saidani; Mohamed Atri

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High-level design for image processing on FPGA using Xilinx AccelDSP

Yahia Said, Taoufik Saidani and Mohamed Atri

The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings, p.1

01/01/2014

Abstract

Conference Title: 2014 World Congress on Computer Applications and Information Systems (WCCAIS) Conference Start Date: 2014, Jan. 17 Conference End Date: 2014, Jan. 19 Conference Location: Hammamet, Tunisia This paper presents the design and implementation of image processing application on field programmable gate array (FPGA). To improve the implementation time, Xilinx AccelDSP, a software for generating hardware description language (HDL) from a high-level MATLAB description has been used. An FPGA-based architecture for Color Space Conversion has been proposed. The design was implemented on Spartan 3A DSP and Virtex 5 devices. Obtained results are discussed and compared with others architectures.

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Title: High-level design for image processing on FPGA using Xilinx AccelDSP
Creators - without role: Yahia Said
Taoufik Saidani
Mohamed Atri
Publication Details: The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings, p.1
Publisher: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Identifiers: 9919176608331
Academic Unit: Northern Borders University; King Khalid University
Language: English
Resource Type: Conference proceeding