High-performance RF-interconnect for 3D stacked memory

Ahmed Alzahmi; Nahid Mirzaie; Chung-Ching Lin; Insoo Kim; Gyung-Su Byun

doi:10.1109/ISOCC.2017.8368793

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Conference proceeding

High-performance RF-interconnect for 3D stacked memory

Ahmed Alzahmi, Nahid Mirzaie, Chung-Ching Lin, Insoo Kim and Gyung-Su Byun

2017 International SoC Design Conference (ISOCC), pp.109-110

11/2017

DOI: https://doi.org/10.1109/ISOCC.2017.8368793

Abstract

3D ICs

Capacitance

high bandwidth memory (HBM)

Optimization

Radio frequency

RF Transceiver

Three-dimensional displays

Through-silicon vias

through-silicon-via (TSV)

Transceivers

Two dimensional displays

A high-performance 3D RF transceiver with improved through-silicon via (TSV) geometry and matching for future 3D stacked memory has been introduced. It utilizes optimization method to achieve impedance matching and maximize signal integrity. TSV is accurately modeled using 3D EM solver tool (HFSS) with the matching network to generate S-parameter accurately. The proposed transceiver scheme is simulated in 65nm CMOS technology at 1V. The results show that the whole structure consumes 11.32mW and accomplishes data rate of 4Gb/s/pin.

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Details

Title: High-performance RF-interconnect for 3D stacked memory
Creators - without role: Ahmed Alzahmi - Southern Methodist University
Nahid Mirzaie - Southern Methodist University
Chung-Ching Lin - Southern Methodist University
Insoo Kim - Dept. of Medicine, University of Connecticut, Farmington, CT, USA
Gyung-Su Byun - Inha University
Publication Details: 2017 International SoC Design Conference (ISOCC), pp.109-110
Publisher: IEEE
Identifiers: 9933964008331
Academic Unit: University of Tabuk
Language: English
Resource Type: Conference proceeding