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High-speed, area-efficient FPGA-based floating-point multiplier
Conference proceeding

High-speed, area-efficient FPGA-based floating-point multiplier

G.H.A. Aty, A.I. Hussein, I.S. Ashour, M. Mones and ECE-CUFE
Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442), Vol.2003-, pp.274-277
2003
DOI: https://doi.org/10.1109/ICM.2003.237828

Abstract

Design optimization Educational institutions Field programmable gate arrays Floating-point arithmetic Hardware design languages High level languages IEEE members Signal processing Systems engineering and theory Telecommunication computing
In this paper, a floating-point multiplier with high speed and area efficient is presented. The multiplier is designed, optimized, and implemented on an FPGA based system. A comparison between the results of the proposed design and a previously reported one is provided. The effect of rounding on the area, speed, and accuracy for three different configurations is examined.

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