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High-speed method of hardware simulation
Conference proceeding

High-speed method of hardware simulation

Vladimir Hahanov, Eugeniy Kamenuka, Hassan Kteiman, Wade Ghribi, Tamara Radivilova and IEEE
2007 PROCEEDINGS OF THE 9TH INTERNATIONAL CONFERENCE ON THE EXPERIENCE OF DESIGNING AND APPLICATION OF CAD SYSTEMS IN MICROELECTRONICS, pp.222-225
01/01/2007
DOI: https://doi.org/10.1109/CADSM.2007.4297530

Abstract

Computer Science Computer Science, Artificial Intelligence Computer Science, Software Engineering Engineering Engineering, Electrical & Electronic Engineering, Manufacturing Operations Research & Management Science Science & Technology Technology Telecommunications
Hardware implementation of triadic fault-free simulation method HES-MV - Hardware Embedded Simulation based on Multi-Valued alphabet is proposed. This method uses hardware gate and RTL models for large scale digital designs description. Structure solutions for logic elements models implementation are presented. Logic element has two bits for four values encoding for each input or output line of simulated device.

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