High-voltage UMOSFETs in 4H SiC

I.A. Khan; J.A. Cooper; M.A. Capano; T. Isaacs-Smith; J.R. Williams; IEEE

doi:10.1109/ISPSD.2002.1016195

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Conference proceeding

High-voltage UMOSFETs in 4H SiC

I.A. Khan, J.A. Cooper, M.A. Capano, T. Isaacs-Smith, J.R. Williams and IEEE

Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics, pp.157-160

2002

DOI: https://doi.org/10.1109/ISPSD.2002.1016195

Abstract

Annealing

Current density

Electron mobility

Fabrication

Implants

Numerical simulation

Protection

Silicon carbide

Silicon devices

Voltage

We report the design and fabrication of UMOSFETs on 4H-SiC with specific on-resistances of 105.1 m/spl Omega/ cm/sup 2/ at a current density of 100 A/cm/sup 2/ and blocking voltage of 5,050 V. These devices incorporate an extended self-aligned p-bottom implant to protect the gate oxide from high electric fields. A novel shadow implant mask was developed to shield the sidewalls from any unwanted p-bottom implant. These UMOSFETs are also the first to incorporate a post-oxidation anneal (POA) in nitric oxide (NO) to improve the inversion layer electron mobility. A single zone JTE (junction termination extension) with peak blocking voltage of 7,500 V was implemented in the device design.

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Details

Title: High-voltage UMOSFETs in 4H SiC
Creators - without role: I.A. Khan - Purdue University West Lafayette
J.A. Cooper - Purdue University West Lafayette
M.A. Capano - Purdue University West Lafayette
T. Isaacs-Smith
J.R. Williams
IEEE
Publication Details: Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics, pp.157-160
Publisher: IEEE
Identifiers: 9931312208331
Academic Unit: Umm Al Qura University
Language: English
Resource Type: Conference proceeding