Abstract
Domino CMOS logic circuit family rinds a wide variety of applications in microprocessors, digital signal processors, and dynamic memory due to their high speed and low device count. However, there are inevitable problems that degrade the noise immunity of this family; they are the inevitable leakage current and the charge sharing. Added to the draw backs is the relatively large power consumption, especially if compared to the static complementary CMOS logic family. To make the matter worse, these drawbacks are more tactile with the scaling of CMOS technology from one generation to the next. In this paper, the impact of CMOS technology scaling on the performance of domino CMOS logic will be investigated. Specifically, the need to decrease the dynamic power consumption forces the designer to use a lower power-supply voltage. This in turn necessitates the reduction of threshold voltage to maintain the performance with the associated increase in subthreshold leakage current. So, a properly sized PMOS keeper must be used to compensate for this leakage. It will be found that the speed, which is the major advantage of domino logic compared to other logic styles, will degrade with CMOS technology scaling due to the contention current of the keeper.
A technique that extends the life time of domino logic in spite of CMOS technology scaling will be proposed. In fact, this technique aims to alleviate the effects of threshold-voltage reduction and the associated increase in subthreshold leakage on the noise immunity and the size of the PMOS keeper through the use of a current sensing circuit. This technique will be simulated for the 0.13 mu m technology with power-supply voltage, V-DD=1.2 V. Simulation results show that the proposed technique enhances the noise margin by approximately 560 mV and enhances the speed by approximately 56% compared to the conventional technique in which the gate of the PMOS keeper is connected to the output terminal, however, at the cost of an area penalty.