Abstract
JPEG2000 has recently become one of the most rewarding image coding standards [1]. It provides a practical set of features which weren't necessarily available in the previous standards. The features were realized as a result of two new techniques, namely the Discrete Wavelet Transform (DWT), and Embedded Block Coding with Optimized Truncation (EBCOT). The complexity of EBCOT Tier-1 makes its hardware implementations very difficult [4] [5] [7] [8]. In this paper, we propose a new simplified architecture for the JPEG2000 MQ-Coder, as the primary section of EBCOT Tier 1. The design is for a complete EBCOT Tier-1 process, and considers system-level issues such as the need for buffeting. Hardware architecture for the proposed process was developed, realized in VHDL, and synthesized for implementation on FPGA Xilinx.