Abstract
The exploitation of Computer Aided Design (CAD) solutions has allowed for the development of many advances toward debugging of very-large-scale integration (VLSI) digital circuits. However, many of the established verification and debugging methods are limited to producing lists of error locations without automatic identification of design corrections. Here, we introduce an automatic correction algorithm (ACM) using an improved in-circuit mutation technique as well as improved parallel distribution of test patterns through the debugging circuit in order to generate unit clauses (UCs) using the NVidia Compute Unified Device Architecture (CUDA). Comparative analysis demonstrates that our proposed algorithm efficiently targets single design bugs of type - gate replacements in several VLSI digital circuits from ISCAS'85 and ISCAS'89 benchmarks with high performance and 100% accuracy. The proposed autocorrection algorithm with serial distribution of test patterns has achieved 5.92x speed-up using ISCAS'85 benchmark and ISCAS'89 benchmark in comparison to previously published mechanism. In addition, the combination of improved in-circuit mutation mechanism and parallelization of distributing test patterns delivers about 11.66x speed-up using ISCAS'85 and ISCAS'89 benchmarks compared to the latest existing correcting methods.