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Improved StrongARM Latch Comparator: Design, Analysis and Performance Evaluation
Conference proceeding

Improved StrongARM Latch Comparator: Design, Analysis and Performance Evaluation

Abdullah Almansouri, Abdullah Alturki, Abdullah Alshehri, Talal Al-Attar, Hossein Fariborzi and IEEE
2017 13TH CONFERENCE ON PH.D. RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME), pp.89-92
01/01/2017

Abstract

Engineering Engineering, Electrical & Electronic Science & Technology Technology
This paper presents an improved StrongARM latch comparator, designed and simulated in 90nm and 32nm CMOS technologies. The proposed design provides an improvement of 7% in energy efficiency, 14% in speed and an average reduction of 41% in the clock feedthrough, compared to the conventional design. The new architecture also minimizes the area by reducing the required transistors needed for the enhanced performance.

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