Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns

M.M. Hafizur Rahman; M. Ghosh; S. Horiguchi; IEEE; M. M. Hafizur Rahman

doi:10.1109/ICECE.2006.355696

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Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns

M.M. Hafizur Rahman, M. Ghosh, S. Horiguchi, IEEE and M. M. Hafizur Rahman

2006 International Conference on Electrical and Computer Engineering, pp.573-576

12/2006

DOI: https://doi.org/10.1109/ICECE.2006.355696

Abstract

bit-flip traffic pattern

Computer networks

Computer simulation

Concurrent computing

deadlock-free routing

Hardware

HTN

inter-processor communication performance

Mesh networks

Multiprocessor interconnection networks

Routing

System recovery

Telecommunication traffic

Traffic control

In this paper, we present a deadlock-free routing algorithm for the hierarchical torus network (HTN) using 2 virtual channels - 2 being the minimum number for dimension order routing - and evaluate the network's inter-processor communication performance under the bit-flip traffic pattern using the proposed routing algorithm. We evaluate the inter-processor communication performance of HTN, H3D-mesh, TESH, mesh, and torus network by computer simulation. It is shown that the inter-processor communication performance of the HTN is better than that of the H3D-mesh, TESH, mesh, and torus networks.

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Title: Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns
Creators - without role: M.M. Hafizur Rahman - Dept. of Comput. Sci. & Eng., KUET, Khulna
M. Ghosh - Khulna University
S. Horiguchi - GSIS, University of Tohoku, Sendai, Japan
IEEE
M. M. Hafizur Rahman - King Faisal University
Publication Details: 2006 International Conference on Electrical and Computer Engineering, pp.573-576
Publisher: IEEE
Identifiers: 9920118308331
Academic Unit: King Faisal University
Language: English
Resource Type: Conference proceeding