Interconnect peak current reduction for wavelet array processor using self-timed signaling

P. Liljeberg; I.B. Dhaou; J. Plosila; J. Isoaho; H. Tenhunen

doi:10.1109/ISCAS.2002.1010498

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Interconnect peak current reduction for wavelet array processor using self-timed signaling

P. Liljeberg, I.B. Dhaou, J. Plosila, J. Isoaho and H. Tenhunen

2002 IEEE International Symposium on Circuits and Systems (ISCAS), Vol.4, pp.IV-IV

2002

DOI: https://doi.org/10.1109/ISCAS.2002.1010498

Abstract

Clocks

Crosstalk

Discrete wavelet transforms

Filter bank

Noise reduction

Power supplies

Power system interconnection

Process design

Signal processing

System-on-a-chip

This paper describes a method for reducing the interconnection peak current in a system-on-chip design. The method is applied to a globally asynchronous locally synchronous 128-point wavelet processor array design with 1.45 million equivalent gates. In the proposed approach, data transfer along buffered highly capacitive on-chip interconnects is realized using asynchronous communication channels. These channels are managed by a global self-timed controller which allows only one channel to be active at a time. This method reduces the interconnect peak current by 75% compared to a design where wires are driven synchronously. This approach allows the reduction of the area devoted to the decoupling capacitance needed to suppress power supply noise.

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Title: Interconnect peak current reduction for wavelet array processor using self-timed signaling
Creators - without role: P. Liljeberg - Dept. of Inf. Technol., Turku Univ., Finland
I.B. Dhaou
J. Plosila
J. Isoaho
H. Tenhunen
Publication Details: 2002 IEEE International Symposium on Circuits and Systems (ISCAS), Vol.4, pp.IV-IV
Publisher: IEEE
Identifiers: 9914197708331
Academic Unit: Dar Al Hekma University
Language: English
Resource Type: Conference proceeding