Abstract
The significance of optimization of gate source/drain extension region (also known as underlap design) in double gate (DG) silicon-on-insulator (SOI) FETs to improve the linearity performance of a low power folded cascode operational transconductance amplifier (OTA) is described. Based on a new figure-of-merit (FoM) involving A(V), linearity, f(T) and de power consumption P-DC the paper presents guideline for optimum design for underlap spacer s and film thickness T-si to maximize the performance of OTA. It has been shown that FoM exhibited by an underlap DG MOSFET OTA gives significantly higher value ( congruent to 9) compared to a conventional single gate bulk MOSFET OTA. This is due to a combination of both higher, f(T), and higher gain A(V) for the same linearity at low power consumption of 360 mu W. With gate length scaling, FoM continues to improve, primarily due to higher value of f(T). A scaled bulk MOSFET OTA exhibits similar but much smaller enhancement in trend for FoM