Abstract
In CMOS technology AND-OR combination logic is used because of the ease of its minimization using different established methodologies such as K-map. On the other hand, majority gate-based logic is not handled well in standard CMOS technologies, primarily because of the hardware inefficiencies in creating majority gates. As a result no optimization techniques of circuits based on majority gates were established. Emerging technologies specifically, quantum-dot cellular automata (QCA) uses majority gate as a fundamental logic primitive instead of the AND-OR combination gates. We report an intuitive systematic methodology J-map minimization technique for reduction of 3-variable Boolean functions into a simplified majority representation. The main contribution of this work is the general and systematic way the new approach can be applied. All attempts in the literature were complex and lacked the systematic approach we are offering. The design of full adder cell will be presented using the new technique.