Limits on Voltage Scaling for Caches Utilizing Fault Tolerant Techniques

Mohammad A. Makhzan; Amin Khajeh; Ahmed Eltawil; Fadi Kurdahi; IEEE

doi:10.1109/ICCD.2007.4601943

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Conference proceeding

Limits on Voltage Scaling for Caches Utilizing Fault Tolerant Techniques

Mohammad A. Makhzan, Amin Khajeh, Ahmed Eltawil, Fadi Kurdahi and IEEE

2007 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, VOLS, 1 AND 2, pp.488-495

Proceedings IEEE International Conference on Computer Design

01/01/2007

DOI: https://doi.org/10.1109/ICCD.2007.4601943

Abstract

Computer Science

Computer Science, Information Systems

Engineering

Engineering, Electrical & Electronic

Science & Technology

Technology

This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume little energy, but enable the system to operate correctly and boost the system performance to close to defect free operation. Overall, power savings of over 40% are reported on standard benchmarks.

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Title: Limits on Voltage Scaling for Caches Utilizing Fault Tolerant Techniques
Creators - without role: Mohammad A. Makhzan - University of California, Irvine
Amin Khajeh - University of California, Irvine
Ahmed Eltawil - University of California, Irvine
Fadi Kurdahi - University of California, Irvine
IEEE
Publication Details: 2007 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, VOLS, 1 AND 2, pp.488-495
Series: Proceedings IEEE International Conference on Computer Design
Publisher: IEEE
Number of pages: 8
Identifiers: 9943731308331
Academic Unit: King Abdullah University of Science & Technology
Language: English
Resource Type: Conference proceeding