Abstract
Conference Title: 2013 Annual IEEE India Conference (INDICON) Conference Start Date: 2013, Dec. 13 Conference End Date: 2013, Dec. 15 Conference Location: Mumbai, India This work presents the linearity characterization by varying the process parameters of new underlap Silicon-on-Insulator (SOI) MOSFETs (with high-k stack on spacer) in single gate (SG) and double gate (DG) configurations. Using linearity defined in-terms of third order intercept (IP3), the paper presents guideline for optimum value of spacer "s", film thickness "Tsi"and doping gradient "d" to maximize the linearity of new underlap design. Based on a new Figure-of-Merit (FoM) involving intrinsic gain Av, IP3, maximum oscillation frequency fMAX and dc power consumption PDC, it has been found that FoM in DG configuration is almost three times higher than that of SG design. This is due to a combination of higher value of fMAX, Av and IP3 in DG configuration with power consumption of ∼ 2.1 mW. The higher value of FoM in DG device has been achieved at similar "on" to "off" current ratio (Ion/Ioff) as specified in current International Technology Road map for Semiconductors (ITRS). [PUBLICATION ABSTRACT]