Abstract
Conference Title: 2017 IEEE International Symposium on Circuits and Systems (ISCAS) Conference Start Date: 2017, May 28 Conference End Date: 2017, May 31 Conference Location: Baltimore, MD, USA Cipher-based message authentication code, CMAC, is a NIST approved standard for checking message integrity and authentication. This work presents a low-latency AES architecture for CMAC. The architecture uses intensive parallel processing per round and takes advantage of the BRAM present in modern FPGA. Experimental results show that for typical IoT application, the proposed architecture has a latency of 10 clock cycles, consumes 1355 slices, 2 BRAMs and achieves a throughput of 3.8Gbps.