Low power 1-Bit full adder using Full-Swing gate diffusion input technique

Omnia Al Badry; M A Abdelghany

Back

Conference proceeding

Low power 1-Bit full adder using Full-Swing gate diffusion input technique

Omnia Al Badry and M A Abdelghany

The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings, p.205

01/01/2018

Abstract

Computer simulation

Delay

Logic

Power consumption

Conference Title: 2018 International Conference on Innovative Trends in Computer Engineering (ITCE) Conference Start Date: 2018, Feb. 19 Conference End Date: 2018, Feb. 21 Conference Location: Aswan, Egypt This paper presents a design which provides full swing output for logic 1 and logic 0 for 1-bit full adder cell and reduces power consumption, delay, and area. In this design full adder consists of two XOR gate cells and one cell of 2×1 multiplexer (MUX). The performance of the proposed design compared with the different logic style for full adders through cadence virtuoso simulation based on TSMC 65nm technology models with a supply voltage of 1v and frequency 125MHz. The simulation results showed that the proposed full adder design dissipates low power, while improving delay and area among all the design taken for comparison.

Metrics

1 Record Views

Details

Title: Low power 1-Bit full adder using Full-Swing gate diffusion input technique
Creators - without role: Omnia Al Badry
M A Abdelghany
Publication Details: The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings, p.205
Publisher: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Identifiers: 9926105208331
Academic Unit: Prince Sattam Bin Abdulaziz University
Language: English
Resource Type: Conference proceeding