Low power 4-Bit Arithmetic Logic Unit using Full-Swing GDI technique

Mahmoud Aymen Ahmed; M A Abdelghany

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Low power 4-Bit Arithmetic Logic Unit using Full-Swing GDI technique

Mahmoud Aymen Ahmed and M A Abdelghany

The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings, p.193

01/01/2018

Abstract

Arithmetic and logic units

Circuit design

Computer simulation

Logic

Multiplexing

Power consumption

Semiconductor devices

Transistors

Conference Title: 2018 International Conference on Innovative Trends in Computer Engineering (ITCE) Conference Start Date: 2018, Feb. 19 Conference End Date: 2018, Feb. 21 Conference Location: Aswan, Egypt Power dissipation and area of the circuit are the main issues in the electronics industry, this paper provides a design of 4-Bit Arithmetic Logic Unit (ALU) using Full-Swing GDI Technique, which considered an effective method for low power digital design while reducing the area of the circuit compared to other logic styles. The proposed ALU design consists of 2×1 Multiplexer, 4×1 Multiplexer and low power Full Adder cell to realize the arithmetic and logic operations. The simulation carried out using Cadence Virtuoso using 65nm TSMC process. The results show that the proposed design consume less power using less number of transistors, while achieving full swing operation compared to previous work.

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Title: Low power 4-Bit Arithmetic Logic Unit using Full-Swing GDI technique
Creators - without role: Mahmoud Aymen Ahmed
M A Abdelghany
Publication Details: The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings, p.193
Publisher: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Identifiers: 9925942808331
Academic Unit: Prince Sattam Bin Abdulaziz University
Language: English
Resource Type: Conference proceeding