Abstract
Conference Title: ESSDERC 2013 - 43rd European Solid State Device Research Conference Conference Start Date: 2013, Sept. 16 Conference End Date: 2013, Sept. 20 Conference Location: Bucharest, Romania Large-area electronics require cost-effective yet precise patterning of electrodes. We demonstrate a simple electrode patterning technique capable of micron-scale gap formation, that allows the patterning of a larger variety of metals than the current portfolio of jettable metallic ink comprises and does not require a high-temperature sintering step. However, this method can produce large variations in gap size resulting in inconsistent and irreproducible transistor drain current. We propose that source-gated transistors (SGTs) are well suited to this technique, as they have a saturated drain current independent of source-drain separation, thus leading to improved current uniformity despite inconsistencies in gap size. [PUBLICATION ABSTRACT]