Abstract
In this paper, behavioral model of a high speed Phase Locked Loop (PLL) based frequency synthesizer is presented which is used for Radio Frequency Identifier (RFID) in UHF carrier. The results are validated through System Vision simulation using Very High Speed Integrated Circuit Hardware Description Language-Analog Mixed Signal (VHDL-AMS). PLL consists of a low jitter PLL employing a Voltage Controlled Crystal Oscillator (VCXO). The advantage of using low-jitter wide-band PLL is excellent performance in terms of jitter and frequency locking. Simulation results are in good agreement with theoretical calculations. Radio Frequency Identification (RFID) uses RF radiation to identify physical objects. With decreasing integrated circuit (IC) cost and size, RFID applications are becoming economically feasible and gaining popularity. In UHF passive RFID tag, communication system needs low-jitter signal for UHF transmitter and receiver to minimize the error in data stream.