Abstract
In this paper, we consider the problem of peak and average power optimization in high-level synthesis. We focus on the scheduling task under timing constraint using supply voltage scaling since it is considered as the most efficient technique for reducing power consumptions in CMOS circuits. We propose a two-phase heuristic for peak and average power minimization using multiple supply voltages scheduling technique. The first phase is the modified power-force-directed scheduling (MPFDS) heuristic based on the well-known force-directed scheduling technique. The second phase is a post-processing procedure (power-area-saving) that is a revisit of the output schedule from the first phase in order to exploit the available rooms to get more power and/or the operating resources minimization. Results show that our proposed heuristic is capable of achieving near-optimal results with polynomial complexity.