Abstract
A flexible architecture is proposed in this paper for implementation Discrete Wavelet Transform (DWT) of 5/3 filter. The proposed architecture includes transforms modules, a RAM and bus interfaces. This architecture works in non separable fashion using a serial-parallel filter with distributed control to compute all the DWT (1D-DWT and 2D-DWT) resolution levels. The so-called lifting scheme represents the fastest implementation of the DWT. A VHDL model was described and synthesized using implementation of our architecture. Synthesis results show that Xilinx XCV600E FPGA implementation can be achieved with a frequency of about 108 Mhz, allowing processing rate between 85 and 187 frames per second for a range of standard picture dimensions. Speed/Area resulting from this processor is analyzed and is shown to demonstrate that our design achieves favourable performances with other FPGA based implementations.