Abstract
Chip (QNoC) is the most effective solution that provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study presents two generic Globally Asynchronous Locally Synchronous (GALS) NoC architectures called GEXPolygon (for Generic EXtanded Polygon.) and GEXSpidergon (for Generic EXtanded Spidergon). These architectures are inspired respectively from the GeNOC and Octagon NoC of TIMA laboratory, and the Spidergon called also STNoC, of STMicroelectronics. GEXSpidergon and GEXPolygon architectures are based on a central router responsible to transfers urgent messages and used in the case of clogging of the close router towards the destination. It comprises multiple interconnected input and output ports and dynamic arbitration mechanisms that resolve any output port conflicts based on the messages priorities. The proposed router is based on a Wormhole commutation technique and the adaptive routing with an efficient path fetching algorithm based on finite state machine to avoid deadlock problems. Handshaking and Aloha protocols are implemented on each router to guarantee the inter routers communication. The proposed router can be also used with other NoC architectures such as the tree and the mesh topologies. The functionalities correctness have been verified by using a traffic generation VHDL based strategy.