Optimization and implementation on FPGA of the DCT/IDCT algorithm

A. Ben Atitallah; P. Kadionik; F. Ghozzi; P. Nouel; N. Masmoudi; Ph Marchegay; IEEE

Back

Conference proceeding

Optimization and implementation on FPGA of the DCT/IDCT algorithm

A. Ben Atitallah, P. Kadionik, F. Ghozzi, P. Nouel, N. Masmoudi, Ph Marchegay and IEEE

2006 IEEE International Conference on Acoustics, Speech and Signal Processing, Vols 1-13, pp.3379-3382

International Conference on Acoustics Speech and Signal Processing (ICASSP)

01/01/2006

Abstract

Acoustics

Computer Science

Computer Science, Artificial Intelligence

Engineering

Engineering, Electrical & Electronic

Imaging Science & Photographic Technology

Science & Technology

Technology

this paper, we present a comparison between two methods, the modified Loeffler algorithm (11 MUL and 29 ADD) and Distributed Arithmetic, to implement the DCT/IDCT algorithm for MPEG or H.26x video compression using VHDL description language. The implementation has been achieved on Altera Stratix EP1S10 FPGA which provides a dedicated DSP blocks required for common signal processing functions. A new solution based on this DSP blocks used for to implement multipliers for the modified Loeffler algorithm in order to optimize speed and area.

Metrics

1 Record Views

Details

Title: Optimization and implementation on FPGA of the DCT/IDCT algorithm
Creators - without role: A. Ben Atitallah
P. Kadionik
F. Ghozzi
P. Nouel
N. Masmoudi
Ph Marchegay
IEEE
Publication Details: 2006 IEEE International Conference on Acoustics, Speech and Signal Processing, Vols 1-13, pp.3379-3382
Series: International Conference on Acoustics Speech and Signal Processing (ICASSP)
Publisher: IEEE
Number of pages: 4
Identifiers: 9912758908331
Academic Unit: Al Jouf University
Language: English
Resource Type: Conference proceeding