Power optimization for video application using clock-gating technique

Lilia Kechiche; Lamjed Touil; Bouraoui Ouni; Abdellatif Mtibaa

doi:10.1109/WSWAN.2015.7210340

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Conference proceeding

Power optimization for video application using clock-gating technique

Lilia Kechiche, Lamjed Touil, Bouraoui Ouni and Abdellatif Mtibaa

2015 2nd World Symposium on Web Applications and Networking (WSWAN), pp.1-7

01/03/2015

DOI: https://doi.org/10.1109/WSWAN.2015.7210340

Abstract

FPGA

Iron

Nickel

Niobium

power optimization

Quantum cascade lasers

real time

video processing

Image and video processing is an important topic that has risen with the digitization of visual content. One of the characteristics of video processing applications is their huge consumption of resources and power. This problem is accentuated especially for mobile devices which have a limited energy supply. In this paper, we propose a method for dynamic power minimization through clock gating technique at the block level. The proposed approach is used for an RGB to HMMD converter and implemented on Virtex-5 FPGA. The obtained results shows a power minimization over 20% with only few added resources.

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Title: Power optimization for video application using clock-gating technique
Creators - without role: Lilia Kechiche - University of Monastir
Lamjed Touil - University of Monastir
Bouraoui Ouni - University of Monastir
Abdellatif Mtibaa - University of Monastir
Publication Details: 2015 2nd World Symposium on Web Applications and Networking (WSWAN), pp.1-7
Publisher: IEEE
Identifiers: 9911731708331
Academic Unit: Taif University
Language: English
Resource Type: Conference proceeding