Abstract
With state of the art technology scaling, the problem of delay variability due to power supply variations is becoming more and more critical. This paper addresses the problem of analyzing the speed degradation in synchronous systems caused by power supply ER-drop in deep submicron CMOS devices. Considering the impact of power supply variation on the clock skew value, violations of the timing constraints equations are presented. To satisfy the timing constraints over a range of 20% of V-DD variation, a 42% increase in the operational clock period has to be met with circuits operating at 2GHz and implemented on 65nm CMOS technology.