Abstract
Conference Title: 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Conference Start Date: 2018, Oct. 26 Conference End Date: 2018, Oct. 30 Conference Location: Chengdu, China This paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC 180nm CMOS technology. The on-chip area and power dissipation of the simulated 3 × 4 TLG array is 1463µm2 and 425µW, respectively.