Reconfigurable latch controllers for low power asynchronous circuits

M. Lewis; J. Garside; L. Brackenbury; IEEE COMP SOC

doi:10.1109/ASYNC.1999.761520

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Conference proceeding

Reconfigurable latch controllers for low power asynchronous circuits

M. Lewis, J. Garside, L. Brackenbury and IEEE COMP SOC

Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp.27-35

1999

DOI: https://doi.org/10.1109/ASYNC.1999.761520

Abstract

Asynchronous circuits

Communication system control

Computer science

Delay

Latches

Logic circuits

Pipelines

Protocols

Signal processing

Timing

A method for reducing the power consumption in asynchronous micropipeline-based circuits is presented. The method is based around a design for latch controllers in which the operating mode of the pipeline latches (normally open/transparent or normally closed/opaque) can be selected according to the dynamic processing demand on the circuit. Operating in normally-closed mode prevents spurious transitions from propagating along a static pipeline, at the expense of reduced throughput. Tests of the new latch controller circuits on a pipelined multiplier datapath show that reductions in energy per operation of up to 32% can be obtained by changing to the normally-closed operating mode. Estimates suggest that in a typical application which exhibits a variable processing demand, a power reduction of between 16-24% is possible, with little or no impact on maximum throughput.

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Details

Title: Reconfigurable latch controllers for low power asynchronous circuits
Creators - without role: M. Lewis - University of Manchester
J. Garside - University of Manchester
L. Brackenbury
IEEE COMP SOC
Publication Details: Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp.27-35
Publisher: IEEE
Identifiers: 9930155708331
Academic Unit: Taibah University
Language: English
Resource Type: Conference proceeding