Abstract
The use of networks on chips has made it possible for computers to perform efficiently and at a high speed. This is because integrated circuits achieve a more elaborate connection between different systems' components. This paper examines the influence of the topology of an interconnection network in parallel computers. Both regular and irregular topologies are explored in an attempt to discover the advantages and disadvantages of each type. In addition, several regular and irregular topologies are investigated. The findings of this study assert that irregular topologies are more efficient than irregular topologies when it comes to performance. The results further suggest that irregular topologies are generally more efficient in some aspects such as chip area and energy consumption. On the other hand, regular topologies represent a more tempting solution when reusability and simplicity are primary concerns. Moreover, this study offers new insights into the functioning of both regular and irregular topologies in networks on chips.