Abstract
We study the Field Programmable Gate Array (FPGA) implementation of fixed width standard and truncated multipliers using Very High speed integrated circuit Hardware Description Language and implemented on Spartan-3AN, Virtex and Virtex-E devices. We have achieved remarkable reduction in FPGA resources, power and delay when the full precision of standard multiplier is not required and the truncated multiplier can be implemented with fewer resources. The comparisons of different FPGA devices layout show that the standard multipliers utilize lot of space as compared to truncated multipliers which could be utilized for other embedded resources.