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Sensitive Registers: a Technique for Reducing the Fetch Bandwidth in Low-Power Microprocessors
Conference proceeding

Sensitive Registers: a Technique for Reducing the Fetch Bandwidth in Low-Power Microprocessors

A. Robinson, J. D. Garside and ACM
GLSVLSI'07: PROCEEDINGS OF THE 2007 ACM GREAT LAKES SYMPOSIUM ON VLSI, pp.138-143
01/01/2007

Abstract

Computer Science Computer Science, Hardware & Architecture Engineering Engineering, Electrical & Electronic Science & Technology Technology

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