Abstract
This paper presents ideas for the development of multi-level compact model (CM) approach to variability and reliability for future generation MOS devices/circuits. Important device/circuit/gate figures-of-merit (FOMs) are formulated in multiple abstraction domains with dual-representation as statistical and probabilistic CMs, and reliability CMs are built into the core CM and propagated to circuit/gate levels. Rather than following the traditional "predictive"-CM paradigm to 'chase' a given technology, the innovative ideas promote the notion of "inventive"-CM, in which "stat/prob/rel-CMs" are developed at the multiple device/circuit levels for variability/reliability assessment together with the evolving technology and design, as it is believed that "the best way to predict future is to invent it."