Abstract
Conference Title: 2017 International Conference on Engineering and Technology (ICET) Conference Start Date: 2017, Aug. 21 Conference End Date: 2017, Aug. 23 Conference Location: Antalya, Turkey In the design of current microelectronic systems, low power is extremely needed since it is the key concern for embedded applications. Besides, a faster treatment is definitely required in a word overshadowed by digital technologies. For that, we propose a new design of synchronous circuit based on a detector avoider block that is intended to optimize two important parameters: power and response time, simultaneously. Our proposed design has been implemented and compared to existing ones. The design results have shown a significant gain in terms of dynamic power as well as in terms of response time compared to existing designs, without negatively influencing other constraints. To further improve the efficiency of our method, the gain has been proved by the physical level.