Abstract
Applications such as error detection, cryptography, and data encoding for digital communications employ field polynomial division. For instance, it is the heart of the traditional Extended Euclidean Algorithm (EEA), which performs field inversion for public cryptosystems. The alignment of variables for each cycle of polynomial division requires revaluation of their degrees. Moreover, the unpredictability of this iterative process increases its area-time complexity. In order to make polynomial division over finite fields suitable for VLSI implementations, there were several implicit attempts to implement them in systolic architectures. This paper revisits polynomial division over ternary fields to derive its iterative equations and develop novel hardware architectures based on a former systolic arrays methodology. Finally, the area-time complexity of the resulted designs are analyzed and compared.