Systolic array implementation of 2-D finite memory filters

S.G. Foda; M.I. Elmasry; P. Agathoklis; IEEE

doi:10.1109/PACRIM.1991.160836

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Conference proceeding

Systolic array implementation of 2-D finite memory filters

S.G. Foda, M.I. Elmasry, P. Agathoklis and IEEE

[1991] IEEE Pacific Rim Conference on Communications, Computers and Signal Processing Conference Proceedings, pp.700-703 vol.2

1991

DOI: https://doi.org/10.1109/PACRIM.1991.160836

Abstract

Costs

Digital filters

Equations

Noise measurement

Polynomials

Signal sampling

Stability

State-space methods

Systolic arrays

Time measurement

A scheme of systolic array implementation for recursive two-dimensional finite memory filters in real time is presented. A 2D state space model for recursive finite memory filters is used to derive a pipelined array for real-time implementation. The technique is based on block processing via iteration. The parallel implementation is a broadcast, calculate, and aggregate (BCA) paradigm with a regular communication structure. The processing elements (PEs) are simple and easy to design and verify, which makes the design cost effective.< >

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Title: Systolic array implementation of 2-D finite memory filters
Creators - without role: S.G. Foda - Toronto Metropolitan University
M.I. Elmasry - Toronto Metropolitan University
P. Agathoklis - Toronto Metropolitan University
IEEE
Publication Details: [1991] IEEE Pacific Rim Conference on Communications, Computers and Signal Processing Conference Proceedings, pp.700-703 vol.2
Publisher: IEEE
Identifiers: 9952585008331
Academic Unit: King Saud University
Language: English
Resource Type: Conference proceeding