Abstract
As integrated circuit process technology progresses into the deep sub-micron region, the phenomenon of process variation has a growing impact on the design and analysis of digital circuits and more specifically in the accuracy and integrity of timing analysis methods. The assumptions made by the analytical models, impose excessive and unwanted pessimism in timing analysis. Thus, the necessity of removing the inherited pessimism is of utmost importance in favour of accuracy. In this paper an approach to the common path pessimism removal timing analysis problem, TKtimer, is presented. By utilizing certain key techniques such as branch-and-bound, caching, tasklevel parallelism and enhanced algorithmic techniques, the approach described by this paper is able to handle any type and size of clock network trees and showed 100% accuracy combined with reasonable execution time within a straightforward solution context.