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Thermal, Power, and Performance Shaping of Multicore Floorplans
Conference proceeding

Thermal, Power, and Performance Shaping of Multicore Floorplans

Fadi N. Sibai and IEEE
2010 INTERNATIONAL CONFERENCE ON MICROELECTRONICS, pp.152-155
International Conference on Microelectronics-ICM
01/01/2010
DOI: https://doi.org/10.1109/ICM.2010.5696102

Abstract

Engineering Engineering, Electrical & Electronic Nanoscience & Nanotechnology Science & Technology Science & Technology - Other Topics Technology
In this paper, we explore and evaluate multicore processor architecture and floorplans in light of performance, power, and thermal issues. Cores-out-caches-inside and both interleaved and non-interleaved versions of cores-sandwiched-between-caches approaches are considered, with 3 levels of cache memories and ring and bus-based interconnects.

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