Abstract
Integrated circuit performance and/or reliability can be compromised because of the time-dependent variability observed in ultra-scaled devices, which arises from atomic scale process related variations and aging mechanisms acting during circuit operation. Therefore, extensive characterization and modeling of the nanoscale underlying phenomena is needed, so that their effects could be predicted and propagated to upper (device and circuit) levels, as dictated by the Reliability-Aware Design methodology. This paper is focused on the time-dependent shifts coming from the gate dielectric in MOS devices. Different approaches to characterize (at the nanoscale), model (at device level) and simulate (in a circuit) the related phenomena are reviewed.