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Tin (Sn) for Enhancing Performance in Silicon CMOS
Conference proceeding

Tin (Sn) for Enhancing Performance in Silicon CMOS

Aftab M. Hussain, Hossain M. Fahad, Nirpendra Singh, Gala A. Torres Sevilla, Udo Schwingenschloegl, Muhammad M. Hussain and IEEE
2013 IEEE 8TH NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE (NMDC), pp.13-15
IEEE Nanotechnology Materials and Devices Conference
01/01/2013

Abstract

Engineering Engineering, Electrical & Electronic Materials Science Materials Science, Multidisciplinary Nanoscience & Nanotechnology Science & Technology Science & Technology - Other Topics Technology
We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-K/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon.

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