Abstract
Sorting is widely used in several practical applications such as searching and database. This paper proposes two improved FPGA based architectures for merge sorter that use fewer hardware resources compared to the state-of-the-art. For instance, with 64 sorted records are output per cycle, implementation results of our first proposal show an improvement in the required number of Flip Flops (FFs) and Look-Up Tables (LUTs) by 84.4% and 77.7%, respectively over the state-of-the-art. Besides, the throughput of our merge sorter is 1.065x higher than that of state-of-the-art. As for the second proposal, a significant improvement is achieved by 66.3% and 84.6% for the needed FFs and LUTs, respectively. Moreover, while our second proposed merge sorter uses significantly fewer resources, it achieves about 95.9% of the performance of state-of-the-art merge sorter.