Abstract
This paper addresses a study of output voltage of a switched capacitor step down converter for a high voltage application. The proposed design is 3: 4 Series to parallel switched capacitor converter based on capacitors and switches only. The Slow Switching Limit Impedance was theoretically calculated and proven. The Slow Switching Limit Impedance has an inverse relation with switching frequency and the capacitor's size. A minimum value of the Slow Switching Limit Impedance is desired; however, that requires a high switching frequency. Increasing the switching frequency might produce losses from switching devices. To maintain the output voltage by keeping switching losses low, a wide bandgap silicon carbide SiC MOSFET was used in this work. The output voltage and its ripple were tested and compared when ideal switches or SiC MOSFET was used. The comparison between ideal switches and SiC MOSFET was applied under several values of the switching frequency. When the increases, a SiC MOSFET successfully shows its ability to keep the switching losses suitable. The LTspice software have been used to simulate the proposed switched capacitor, and the results have been analyzed and discussed.